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Herbert M. Shapiro - InventionShare. Laguna Niguel, CA, US

Herbert M. Shapiro Herbert M. Shapiro

Invention Advisor | Circuit Seed

Laguna Niguel, CA, UNITED STATES

Herbert M. Shapiro is an Invention Advisor at Circuit Seed

Areas of Expertise (2)

Electrical Engineering

Invention Advisory

Patents (5)

Phase frequency detector and accurate low jitter high frequency wide-band phase …

US20170373697A1

2015 A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

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Oil leak containment system and method

US9890618B1

2014 Apparatus for containing oil and/or gas leakage from a drilling operation (off-shore or on-shore) comprised of an expandable membrane surrounding a central spline, an apparatus adapted to the removal of the captured oil or gas, and a blowout-handling “fuse” capability. The bottom section of the off-shore version includes operator-controlled extension members to expand the membrane to fully surround the drill site. Any further leakage from the well site will further expand the membrane from the spline sections as it moves upward. When the leaked material reaches the top an extraction apparatus included allows it to be extracted safely.

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Pump system suitable as a heart assist device

US5211659A

1990 Artificial heart type devices are made into practical heart assist devices by making the blood chambers of the device disposable or by adapting the blood chambers to accept disposable inserts. The inserts have extensions which protrude through the inlet and outlet ports of the chambers to connect to the blood system of a living body.

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Apparatus and method for forming solder bonding pads

US5873511A

1997 The placement of solder "balls" in a Ball Grid Array is accomplished by placing a solder strip in contact with the top surface of the ball grid array carrier. The pulsing of a laser directed at the solder in discrete positions permits the transfer of the solder to the gold dot, of the array of dots, on the carrier in registry with the laser output when activated. Selective solder placement is possible and increasingly higher throughput is achieved by the use of laser diode bars or optical fiber fans to effect solder transfer to a plurality of dots of the array simultaneously. The entire process can be automated by making the solder strip continuous through a recycling station arranged along a path along which the solder strip moves to the position where the carrier and the solder strip are moved into juxtaposition. The use of a transparent strip with a pattern of holes filled with solder paste permits easy transfer of the solder to the gold dots or islands on the carrier in registry with laser beam.

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Etching technique for fabricating semiconductor or ceramic devices

US3122463A

1961 In its most important aspect, this invention relates to selective etching techniques useful in the manufacture of diffused semiconductor devices. As will become evident, it has wider applicability. In this connection, the term diffused semiconductor device refers to a semiconductor device including a PN junction formed by exposing, at elevated temperatures, portions of the surface of a semiconductor wafer to a vapor of a significmt or conductivity type determining impurity. One of the major continuing problems in the manufacture of a diffused semiconductor device is the control of the geometry of the PN junction included therein. This problem is resolved, at present, by forming a diffusion resistant coating over the surface of a semiconductor wafer and etching a pattern through this resistant layer typically by the known photo-resist technique. For a silicon substnate the resistant layer typically is a thermally grown SiO coating as disclosed in Patent 2,802,- 760, issued August 13, 1957, to L. Derick and C. I. Frosch. The diffusion resistant layer, accordingly, is formed into a mask for a subsequent diffusion step. The underlying semiconductor surface thus is exposed selectively and can be subjected to a vapor of a significant impurity to provide a PN junction of the geometry required.

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