Larry Pileggi
Department Head Professor, Electrical and Computer Engineering Carnegie Mellon University
- Pittsburgh PA
Larry Pileggi is a specialist in the automation of integrated circuits, and developing software tools for the optimization of power grids.
Biography
He received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University in 1989. He has consulted for various semiconductor and EDA companies, and was co-founder of Fabbrix Inc., Extreme DA, and Pearl Street Technologies. His research interests include various aspects of digital and analog integrated circuit design, and simulation, optimization and modeling of electric power systems.
He has received various awards, including Westinghouse corporation’s highest engineering achievement award, a Presidential Young Investigator award from the National Science Foundation, Semiconductor Research Corporation (SRC) Technical Excellence Awards in 1991 and 1999, the FCRP inaugural Richard A. Newton GSRC Industrial Impact Award, the SRC Aristotle award in 2008, the 2010 IEEE Circuits and Systems Society Mac Van Valkenburg Award, the ACM/IEEE A. Richard Newton Technical Impact Award in Electronic Design Automation in 2011, the Carnegie Institute of Technology B.R. Teare Teaching Award for 2013, and the 2015 Semiconductor Industry Association (SIA) University Researcher Award. He is a co-author of "Electronic Circuit and System Simulation Methods," McGraw-Hill, 1995 and "IC Interconnect Analysis," Kluwer, 2002. He has published almost 400 conference and journal papers and holds 40 U.S. patents. He is a fellow of IEEE.
Areas of Expertise
Media Appearances
Useless High-Voltage Power Lines Risk Sparking California Fires
Bloomberg online
2025-02-21
A high-voltage transmission line can transfer electricity to a nearby idled line through a process called electromagnetic induction. The magnetic field generated by a current on the energized line creates a current on other, nearby lines, said Larry Pileggi, a professor of electrical engineering at Carnegie Mellon University. A surge of current could increase the size of the magnetic field, Pileggi said.
AI meets opera: A new blended class at CMU yields insights on music and flow
Pittsburgh Post-Gazette online
2024-04-20
The partnership was a natural fit for a multidisciplinary campus, said Larry Pileggi, who leads CMU’s Department of Electrical and Computer Engineering.
Latency, Interconnects, And Poker
Semiconductor Engineering online
2024-02-20
Semiconductor Engineering sat down with Larry Pileggi, Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University, and the winner of this year’s Phil Kaufman Award for Pioneering Contributions. What follows are excerpts of that conversation.
To Become a World-Class Chipmaker, the United States Might Need Help
The New York Times
2023-11-17
Immigrants helped build Silicon Valley. Andy Grove, for example, escaped from Hungary in 1956 and went on to become the third employee of Intel, building it into a global chipmaking powerhouse. The United States still excels at designing chips but has lost the lead in making them. “Our U.S. work force is of insufficient size, but also, large populations of our technical work force are focused on learning A.I. and software development, which makes immigration of semiconductor technologists even more imperative,” Larry Pileggi, a professor of electrical and computer engineering at Carnegie Mellon University, wrote in an email.
Preparing the Chip Workforce of the Future
Carnegie Mellon University online
2021-04-29
"The ECE has shown industry partners the trends that are occurring at all major universities regarding the decline in students who choose hardware design as their specialty — and specifically, the trends for students who specialize in integrated circuit design," said Larry Pileggi, department head of ECE.
Media
Social
Industry Expertise
Accomplishments
Phil Kaufman Award for Pioneering Contributions
2024
Semiconductor Industry Association (SIA) University Researcher Award
2015
Carnegie Institute of Technology B.R. Teare Teaching Award
2013
ACM/IEEE A. Richard Newton Technical Impact Award in Electronic Design Automation
2011
IEEE Circuits and Systems Society Mac Van Valkenburg Award
2010
Education
Carnegie Mellon University
Ph.D.
Electrical and Computer Engineering
1989
University of Pittsburgh
M.S.
Electrical Engineering
1984
University of Pittsburgh
B.S.
Electrical Engineering
1983
Articles
Large Scale Bilevel Optimization for NK SCOPF Using Adversarial Robustness
IEEE Transactions on Power Systems2025
Ensuring a secure dispatch against multiple simultaneous outages has long been desired to maintain grid security in the presence of severe events, such as extreme weather phenomena. Traditionally denoted as N-k security constrained optimal power flow (N-k SCOPF), this problem is intractable to solve due to its size being combinatorial in the number of simultaneous outages and due to the non-convex nature of the AC network constraints. This hinders the use of N-k SCOPF for operating realistic-scale systems. In this paper, we introduce a methodology to scalably solve an AC-feasible dispatch that improves security over simultaneous outages. Our methodology poses N-k SCOPF as a bilevel optimization problem and solves it using an adversarial robustness approach.
Contingency analysis with warm starter using probabilistic graphical model
Electric Power Systems Research2024
Cyberthreats are an increasingly common risk to the power grid and can thwart secure grid operations. We propose to extend contingency analysis to include cyberthreat evaluations. However, unlike the traditional N-1 or N-2 contingencies, cyberthreats (eg, MadIoT) require simulating hard-to-solve Nk (with k≫ 2) contingencies in a practical amount of time. Purely physics-based power flow solvers, while being accurate, are slow and may not solve Nk contingencies in a timely manner, whereas the emerging data-driven alternatives are fast but not sufficiently generalizable, interpretable, and scalable. To address these challenges, we propose a novel conditional Gaussian Random Field-based data-driven method that performs fast and accurate evaluation of cyberthreats. It achieves speedup of contingency analysis by warm-starting simulations, ie, improving starting points, for the physical solvers.
Generalized smooth functions for modeling steady-state response of controls in transmission and distribution
Electric Power Systems Research2022
The promise of renewables and the consequent fluctuations in the power grid necessitate a robust simulation framework to capture the steady-state behavior of new controls. However, standard non-differentiable models of control mechanisms produce divergence and/or numerical oscillations in large power flow simulations. In this paper, we describe a methodology that introduces two generalized class C1 smooth basis functions to model the steady-state of various controls in power flow for transmission and three-phase distribution as well as optimization settings. These models are accompanied by homotopy methods and limiting techniques in the simulation engine that ensure scalable and robust convergence.
Efficient steady state analysis of the grid using electromagnetic transient models
Electric Power Systems Research2022
Modern grids contain an increasing number of non-linear grid devices that are accurately modeled only in the time domain. Performing an accurate steady-state analysis with such models requires a transient simulation to infinite (sufficiently long) time, which can be computationally prohibitive. Power flow provides an efficient, but approximate steady state analysis using models based on a single nominal frequency, which fails to represent the true steady-state. We present a new method for efficiently analyzing the steady state response using traditional transient models that is inspired by harmonic balance methods. Rather than solving the underlying ODE by discretizing time, our method iterates on the entire waveform to find an accurate time domain waveform that captures the steady-state dynamics for all three phases.
Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip
Journal of Micro/Nanolithography, MEMS, and MOEMS2014
For the past four decades, cost and features have driven complementary metal-oxide semiconductor (CMOS) scaling. Severe lithography and material limitations seen below the 20-nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of sub-20-nm CMOS. For affordable scaling, it is imperative to work past sub-20-nm technology impediments while exploiting its features. To this end, we propose to broaden the scope of design technology co-optimization (DTCO) to be more holistic by including microarchitecture design and computer-aided design, along with circuits, layout, and process technology.
