Industry Expertise (3)
Areas of Expertise (3)
University of Virginia: Ph.D., Electrical Engineering 2004
University of Virginia: M.S., Electrical Engineering 2003
Washington University in St. Louis: B.S., Electrical Engineering 1997
Central College: B.A., Physics 1996
Selected Articles (5)
We have studied the effect of low energy (30 keV) electron beam exposure on carbon nanotube field-effect transistors, using an electron beam lithography system to provide spatially controlled dosage. We show that reversible tuning of the transport behavior is possible when a backgate potential is applied during exposure. n-type behavior can be obtained by electron beam exposure of a device with positive gate bias, while ambipolar behavior can be obtained via negative gate bias. The observed transport behavior is relatively stable in time. We propose possible mechanisms for the observed phenomena and suggest directions for further research.
The implementation of circuit architectures based on molecular electronic devices has been impeded by the availability of facile fabrication schemes for the interconnection of individual devices. The deposition and patterning of a top contact layer between adjoining devices for interconnection purposes can result in contacts of poor fidelity, which introduces artifacts in the I-V characteristics that are not attributable to molecular transport between the contacts. In this study, through the fabrication of interconnected devices within the crossbar device architecture, we demonstrate that the vapor-phase molecular deposition method for fabrication of device layers was compatible with the massively parallel microelectronic fabrication process of liftoff, for patterning of contact layers. A prepatterned device with Au bottom contacts, as well as a bilayer resist for patterning the top Au contacts through postdeposition liftoff was used as the substrate for vapor-phase deposition of a monolayer of conjugated oligo-(phenylene ethynylene) (plain-OPE) molecules and patterning of the top metal contact layer. Interconnection in series and parallel configurations was confirmed by I-V characteristics similar to classical resistors with equivalent conductivity of each individual molecular device. Additionally, to better understand molecular transport in the device junctions, we performed temperature-dependent I-V studies on individual molecular devices that were fabricated using prepatterned Au bottom contacts as the substrate for solution-phase deposition of the molecular monolayer, onto which the Au top contacts were evaporated and patterned using a shadow mask. Molecular layers of two distinctly different room-temperature I-V characteristics, including nonswitching plain-OPE and switching nitro-OPE molecular devices, were used to study the fidelity of the molecular junctions. Based on the persistence of the device characteristics of both types of molecular layers down to 100 K, and in particular, the observation of switching between "high" and "low" conductivity states at characteristic threshold voltages at all temperatures, only with nitro-OPE molecular devices, and not with plain-OPE molecular devices, we conclude that the observed transport was a characteristic molecular signature not dependent on filament formation at contacts.
The field of molecular electronics is often limited by nonreproducible electrical device characteristics and low yields of working devices. These limits may result from inconsistencies in the quality and structure of the monolayers of molecules in the devices. In response, the authors have developed an ultrahigh vacuum vapor phase deposition method that reproducibly assembles monolayers of oligo(phenylene ethynylene) molecules (the chemical backbone of many of the molecules used in molecular electronics). To improve the structure and purity of the monolayer, the vapor phase assembly is performed in an ultrahigh vacuum environment using a low temperature organic thermal cell. Because vapor phase assembly does not require the use of solvents, a potential source of contamination is eliminated. The absence of solvents also permits the fabrication of complex device architectures that require photoresist patterning prior to the molecular assembly. Characterization via ellipsometry,x-ray photoelectron spectroscopy, and scanning tunneling microscopy shows that the monolayers are dense, chemisorbed, ordered, and chemically pure.
Giant magnetoresistive (GMR) materials-based magnetic random access memory (MRAM) has become attractive due to non-volatility, speed and density1. The vertical MRAM (VMRAM) design model shows good signal level and high speed and density potential. The memory cell for the VMRAM model is a ring shaped magnetic material multilayer, which ensures high repeatability and low switching energy. This GMR structure, however, is difficult to pattern as it contains materials such as Ni, Fe, Co, and Cu, which are difficult to dry etch because they lack volatile etch products. This work shows that it is possible to overcome the difficulties associated with etching GMR materials by using hydrogen silsesquioxane (HSQ) as an etch mask. We have used HSQ in a direct-write electron-beam lithography system with a dose of 600 μC/cm2, and in a Ga+ ion focused ion beam (FIB) system with a dose of 12 μC/cm2. Both are followed by development and an argon plasma etch at 10mTorr and 100W RIE power. The HSQ layer provides high resolution as well as good etching resistance. Electron-beam exposed HSQ shows a 1:1.5 selectivity over the GMR film stack and the FIB exposed HSQ showed an improved etch selectivity of 1:1. Ring shaped GMR structures with a 75/225 nm (ID/OD) have been fabricated, which corresponds to a memory density of 4Gb/in2.
The most difficult aspects in manufacturing a reflective slit substrate are achieving a precisely fabricated slit surrounded by an optically flat surface. A commonly used technique is to polish a metal substrate that has a slit cut by electric discharge machine (EDM) methods. This process can produce 'optically flat' surfaces; however, the EDM can produce a slit with edge roughness on the order of 10 microns and a RMS field roughness of ~1 micron. Here, we present a departure from these traditional methods and employ the advantages inherent in integrated circuit fabrication. By starting with a silicon wafer, we begin with a nearly atomically flat surface. In addition, the fabrication tools and methodologies employed are traditionally used for high precision applications: this allows for the placement and definition of the slit with high accuracy. If greater accuracy in slit definition is required, additional tools, such as a focused ion beam, are used to define the slit edge down to tens of nanometers. The deposition of gold, after that of a suitable bonding layer, in an ultra-high vacuum chamber creates a final surface without the need of polishing. Typical results yield a surface RMS-roughness of approximately 2nm. Most of the techniques and tools required for this process are commonly available at research universities and the cost to manufacture said mirrors is a small fraction of the purchase price of the traditional ones.