Prabhat Mishra is a professor in the Department of Computer and Information Science and Engineering and a UF Research Foundation professor, where he leads the CISE Embedded Systems Lab. His research interests include embedded and cyber-physical systems, hardware security and trust, computer architecture, energy-aware computing, formal verification, system-on-chip validation, machine learning and quantum computing.
Areas of Expertise (6)
Real-time detection and localization of DoS attacks in NoC based SoCsDesign, Automation And Test in Europe
Subodha Charles, et. al
Network-on-Chip (NoC) is widely employed by multi-core System-on-Chip (SoC) architectures to cater to their communication requirements. The increased usage of NoC and its distributed nature across the chip has made it a focal point of potential security attacks. Denial-of-Service (DoS) is one such attack that is caused by a malicious intellectual property (IP) core flooding the network with unnecessary packets causing significant performance degradation through NoC congestion.
Security-aware FSM design flow for identifying and mitigating vulnerabilities to fault attacksIEEE Transactions on Computer-aided design of integrated circuits and systems
Adib Nahiyan, et. al
The security of a system-on-chip (SoC) can be compromised by exploiting the vulnerabilities of the finite state machines (FSMs) in the SoC controller modules through fault injection attacks. These vulnerabilities may be unintentionally introduced by traditional FSM design practices or by CAD tools during synthesis. In this paper, we first analyze how the vulnerabilities in an FSM can be exploited by fault injection attacks.
Scalable test generation for Trojan detection using side channel analysisIEEE Transactions on Information Forensics and Security
Yuanwen Huang, et. al
Hardware Trojan detection has emerged as a critical challenge to ensure security and trustworthiness of integrated circuits. A vast majority of research efforts in this area has utilized side-channel analysis for Trojan detection. Functional test generation for logic testing is a promising alternative but it may not be helpful if a Trojan cannot be fully activated or the Trojan effect cannot be propagated to the observable outputs.