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Robert C. Schober - InventionShare. Orange County, CA, US

Robert C. Schober Robert C. Schober

Co-Founder | Circuit Seed

Orange County, CA, UNITED STATES

Robert C. Schober is an expert in integrated circuit design

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Biography

Bob Schober has been a leader in ultra-low power integrated circuits starting from the beginning of his professional career in spacecraft electronic design, through extensive work in integrated circuit design for the cardiac pacing industry from 1975 to 1999 to his current work in IC design today. Mr. Schober's experience has been primarily in the field of analog/digital integrated circuit design. Starting in the early 1960's, Bob worked as an electrical engineer for General Electric Space and Missile Systems; a senior engineer for Martin Marietta Corporation; a member of the technical staff for Hughes Aircraft Corporation; a senior member of the technical staff at TRW Systems; a senior member of the technical staff at California Institute of Technology Jet Propulsion Laboratory; and a principal engineer at American Hospital Supply Corporation’s Edward's Pacemaker Systems including American Hospital’s Corporate Research Center. Mr. Schober received a special award as the highest individual contributor in the history of American Hospital Supply. In 1982, Mr. Schober has been a founder of many successful startups including Biomedical LSI, NanoPower, Inc., Innurvation, and Circuit Seed.

The primary focus of Bob's work has been the design of low power, high reliability circuits, most of which have been analog. Mr. Schober has also performed digital design and layout of digital systems up to and including custom microprocessors, direct memory access controllers, and floating point processors. In addition, he has designed and laid out multiple-giga-sample flash mode Gallium-Arsenide Analog to Digital Converters’ and numerous Radio Frequency integrated circuits. Mr. Schober holds multiple patents in the areas of cardiac pacemakers, high efficiency/compact digital integrated circuit cell libraries, RF, and high sensitivity RFID integrated circuits, as well as multiple patent applications in the area of endoscopic pill cameras.

Areas of Expertise (6)

Complementary Current Field Effect Transistor (CiFET)

Application-Specific Integrated Circuit (ASIC)

Analog & Digital IC Design

RF Analog Desings

CMOS

Mixed Signal

Education (1)

Widener University: BS, Electrical Engineering

Patents (40)

COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

WO2017019064

2017-02-02

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

US10211781

2019-02-19

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

EP3329598

2018-06-06

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

CA3031736

2017-02-02

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

CN10814121

2018-06-08

本发明涉及新颖及发明性复合装置结构,从而实现利用亚阈值操作的基于电荷的方法,以用于设计模拟CMOS电路。确切地说,本发明涉及基于对互补n型及p型电流场效应晶体管的固态装置,所述电流场效应晶体管中的每个具有两个控制端口,亦即低阻端口和栅控端口,而常规固态装置具有个控制端口,亦即栅控端口。这种新颖固态装置提供优于所述常规装置的各种改良。

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

KR20180034555

2018-04-04

본 발명은, 아날로그 CMOS 회로를 설계하기 위한, 서브-문턱 동작(sub-threshold operation)의 이점을 갖는 전하 기반 접근법을 가능하게 하는 신규하고 독창적인 복합 소자 구조에 관한 것이다. 특히, 종래의 고체 상태 소자는 하나의 제어 포트, 즉, 게이트 제어 포트를 갖는 반면, 본 발명은 두 개의 제어 포트, 즉, 저 임피던스 포트 및 게이트 제어 포트를 각각 갖는 n-형 및 p-형 전류 전계효과 트랜지스터의 상보적 쌍에 기초한 고체 상태 소자에 관한 것이다. 이 신규한 고체 상태 소자는 종래의 소자에 비해 다양한 개선을 제공한다.

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

WO2017105554

2017-06-22

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuites.

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

US10283506

2019-05-07

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

CN108140613

2018-06-08

本发明涉及对基于新颖及创造性复合装置结构的电流场效应晶体管和跨阻抗MOS装置的改进,所述复合装置结构实现基于电荷的利用亚阈值操作的方法,所述方法用于设计模拟CMOS电路。本发明进步涉及过饱和电流场效应晶体管(xiFET),其具有源极、漏极、扩散、第栅极和第二栅极端子,其中源极沟道界定于所述源极端子与所述扩散端子之间,漏极沟道界定于所述漏极端子与所述扩散端子之间。所述第栅极端子电容耦合到所述源极沟道;且所述第二栅极端子电容耦合到所述漏极沟道。所述扩散端子接收引起整个所述源极和漏极沟道中的扩散电荷密度的改变的电流。所述xiFET提供用于设计各种模拟电路的基本构建块。

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

WO2017019973

2017-02-02

The present invention relates to a multi-stage and feed forward compensated complimentary current field effect transistor amplifiers, enabling a charge-based approach that takes advantage of the exponential properties incurred in sub-threshold operation. A plurality of complimentary pairs of novel current field effect transistors are connected in series to form a multi-stage amplifier.

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

US20180226930

2018-08-09

The present invention relates to a multi-stage and feed forward compensated complimentary current field effect transistor amplifiers, enabling a charge-based approach that takes advantage of the exponential properties incurred in sub-threshold operation. A plurality of complimentary pairs of novel current field effect transistors are connected in series to form a multi-stage amplifier.

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

CN108141181

2018-06-08

本发明涉及种多级式且前馈补偿的互补电流场效应晶体管放大器,实现利用在亚阈值操作中引发的指数属性的基于充电的方法。新颖电流场效应晶体管的多个互补对串联连接以形成多级放大器。

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

WO2017019978

2017-02-02

The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET), and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel / W/L of drain channel).

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

US20180219519

2018-08-02

The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

CN108141180

2018-06-08

本发明涉及种用于低噪声电流放大器或跨阻抗放大器的新颖和创造性的复合装置结构。所述跨阻抗放大器包含:放大器部分,所述放大器部分使用对互补的新颖n型和p型电流场效应晶体管(NiFET和PiFET)来将电流输入转换为电压;以及使用另对互补的NiFET和PiFET的偏置产生部分。可通过源极沟道的宽度(W)长度(L)比与漏极沟道的宽度(W)长度(L)比的比率(源极沟道的W/L/漏极沟道的W/L)来配置和编程NiFET和PiFET的跨阻抗以及其增益。

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

WO2017019981

2017-02-02

Existing proportional to absolute temperature (PTAT)/ complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

US20180224878

2018-08-09

Existing proportional to absolute temperature (PTAT)/complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

CN108140614

2018-06-08

现有的与绝对温度成比例(PTAT)/与绝对温度互补(CTAT)参考电压电路需要种对准确度和对温度及湿度的不符合要求的灵敏度误差或变化进行匹配的较大组件计数和占地面积的精确装置。本发明涉及种用于这种基于对自偏置互补的n型和P型电流场效应晶体管的参考电压电路的新颖方法,所述方法提供轨道PTAT、轨道CTAT和模拟参考电压。

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SCALABLE INTEGRATED DATA CONVERTER

WO2017106835

2017-06-22

The present invention relates to an integrated data converter, in particular analog to digital converters (ADC) and digital to analog converters (DAC), using a charge-based approach. Complimentary pairs of current field effect transistors are used to form amplifiers for forming scalable ADCs and DACs are disclosed, including successive approximation data converters (ADCs and DACs), and pipe-lined data converters (ADCs and DACs).

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SCALABLE INTEGRATED DATA CONVERTER

EP3391544

2018-10-24

The present invention relates to an integrated data converter, in particular analog to digital converters (ADC) and digital to analog converters (DAC), using a charge-based approach. Complimentary pairs of current field effect transistors are used to form amplifiers for forming scalable ADCs and DACs are disclosed, including successive approximation data converters (ADCs and DACs), and pipe-lined data converters (ADCs and DACs).

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SCALABLE INTEGRATED DATA CONVERTER

CN108702155

2018-10-23

本发明涉及种集成数据转换器,具体地涉及使用基于电荷的方法的模数转换器(ADC)和数模转换器(DAC)。电流场效应晶体管的互补对用于形成可扩展ADC的放大器,并且公开了DAC,包含逐次逼近数据转换器(ADC和DAC)和流水线数据转换器(ADC和DAC)。

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SCALABLE INTEGRATED DATA CONVERTER

JP2019504585

2019-02-14

本発明は、集積データ変換器、特に、電荷に基づく手法を使用する、アナログデジタル変換器(ADC)及びデジタルアナログ変換器(DAC)に関する。スケーラブルADC及びDACを形成するための増幅器を形成するために使用される相補ペアの電流電界効果トランジスタが開示され、これは、逐次比較型データ変換器(ADC及びDAC)、及びパイプライン型データ変換器(ADC及びDAC)を含む。

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LOW NOISE SENSOR AMPLIFIERS AND TRANS-IMPEDANCE AMPLIFIERS USING COMPLEMENTARY PAIR OF CURRENT INJECTION FIELD-EFFECT TRANSISTOR DEVICES

WO2018098389

2018-05-31

This invention relates to low noise sensor amplifiers and trans-impedance amplifiers using a complementary pair of current injection field effect transistor (iFET) devices (CiFET). CiFET includes a N-type current field-effect transistor (NiFET) and a P-type current field-effect transistor (PiFET), each of the NiFET and PiFET has a source, a drain, a gate, and a diffusion (current injection) terminal (iPort). Each iFET also has a source channel with a width and a length between the source and diffusion terminal, and drain channel with a width and a length between the drain and the diffusion terminal. A trans-impedance of the CiFET device is adjusted by a ratio of width / length of source channel over width / length of drain channel of the iFET and supply power voltage. In one configuration, the gate terminals of the NiFET and PiFET are connected together to form a common gate. In another configuration that common gate is configured as a voltage input for a high input impedance mode. Output voltage swings around a common mode voltage.

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

WO2016118936

2016-07-28

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved / addressed by use with a charge transfer-based PLL charge pump.

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

US20170373697

2017-12-28

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

CA2973368

2016-07-28

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved / addressed by use with a charge transfer-based PLL charge pump.

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

WO2016118183

2016-07-28

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

US20180019757

2018-01-18

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

CA2974821

2016-07-28

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

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TRACK AND HOLD CIRCUIT

WO2018200482

2018-12-12

The present invention relates to an improvement to a track and hold circuit. A jitter-free track and hold function independent of signal amplitude is achieved by a circuit which fixes the sample voltage to the charge on a flying sampling capacitor and sets maintains that charge prior to isolation through applying application of the sample voltage to a utilization circuit. This may be done by adding an extra switch to the standard track and hold circuit and operating the switches in a timed sequence manner to provide the sample aperture based on the charge on the flying sampling capacitor common to the circuit.

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CHARGE-BASED PHASE LOCKED LOOP CHARGE PUMP

US8525564

2013-09-03

Charge-based charge pumps are described which include a switchable capacitor configured for connection to a voltage source, a ground, and a charge pump output. A first pair of switches include a first switch configured to connect the switchable capacitor to ground and a second switch configured to connect the switchable capacitor to the voltage source. A second pair of switches include a third switch configured to connect a first node, between the switchable capacitor and ground, to the charge pump output, and a fourth switch configured to connect a second node, between the switchable capacitor and the voltage source, to the charge pump output. Locked loop designs, such as phase locked loops or delay locked loops, are described that include charge-based charge pumps.

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FLIP-FLOPS

US6333656

2001-12-25

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.

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PROGRAMMABLE DIGITAL CARDIAC PACER

US4557266

1985-12-10

A cardiac pacer has separate digital filter circuits for sensing atrial and ventricular activity. Parameter data stored in memory is used by the digital filters for identifying the various components of cardiac activity, such as the P, R and T waves, as well as for identifying Premature Ventricular Contractions (PVC). A Ventricular Rate Time Out period is established from the last natural beat or stimulating pulse; and if a P wave or natural R wave is not sensed during that period, the system generates a stimulating pulse and, using T wave parameters in the ventricular filter, tests to verify capture.

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PROGRAMMABLE DIGITAL CARDIAC PACER

CA1171140

1984-07-17

The specification describes an improved cardiac pacer, and more particularly a pacer which is adapted for implantation in a patient. The cardiac pacer apparatus has an electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window and signal detector means including sensing means for sensing cardiac signals on the electrode means. Filter means including a filter circuit receive the signal sensed by the sensing means for quantizing the sensed signal and continuously generating digital words representative of the slope of the sensed signal over the sample time window. Parameter memory means store signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal. A selection circuit means including a selection circuit responsive to the quantized output signals of the filter means and the stored selection criteria signals generates a detection signal if the digital slope words meet the predetermined selection criteria. Finally generator means generate a stimulating signal and couple the same to the electrode means if the selection circuit means fails to generate the detection signal within a predetermined time from a previous detection signal or a previous stimulating signal.

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MEJORAS EN MARCAPASOS CARDIACO DIGITAL Y PROGRAMABLE

MX150919

1984-08-16

The specification describes an improved cardiac pacer, and more particularly a pacer which is adapted for implantation in a patient. The cardiac pacer apparatus has an electrode means including at least a first electrode adapted to stimulate the heart; control means including timing means which defines a sample time window and signal detector means including sensing means for sensing cardiac signals on the electrode means. Filter means including a filter circuit receive the signal sensed by the sensing means for quantizing the sensed signal and continuously generating digital words representative of the slope of the sensed signal over the sample time window. Parameter memory means store signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal. A selection circuit means including a selection circuit responsive to the quantized output signals of the filter means and the stored selection criteria signals generates a detection signal if the digital slope words meet the predetermined selection criteria. Finally generator means generate a stimulating signal and couple the same to the electrode means if the selection circuit means fails to generate the detection signal within a predetermined time from a previous detection signal or a previous stimulating signal.

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HIGH SENSITIVITY RFID TAG INTEGRATED CIRCUITS

WO2007014053

2009-04-23

A method and apparatus for an ultra-high sensitivity, low cost, passive (no battery) low-power energy harvesting data transmitting circuit energy, such as a RFID (Radio Frequency IDentification) tag integrated circuit 'chip.' By using combinations of special purpose design enhancements, the low-power energy harvesting passive data transmitting circuit, such as the RFID tag chip, operates in the sub-microwatt power range. The chip power should be derived from a low-microwatt per square centimeter RF field radiated to the RFID tag antenna from the tag reader (interrogator) or derived from a suitable low signal source, such as a sonic transducer (e.g., a piezoelectric transducer or a low level DC source, such as a bi-metallic or chemical source).

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SYSTEM AND METHOD FOR ACOUSTIC INFORMATION EXCHANGE INVOLVING AN INGESTIBLE LOW POWER CAPSULE

US20140343378

2014-11-20

A method of communicating with an ingestible capsule includes detecting the location of the ingestible capsule, focusing a multi-sensor acoustic array on the ingestible capsule, and communicating an acoustic information exchange with the ingestible capsule via the multi-sensor acoustic array. The ingestible capsule includes a sensor that receives a stimulus inside the gastrointestinal tract of an animal, a bidirectional acoustic information communications module that transmits an acoustic information signal containing information from the sensor, and an acoustically transmissive encapsulation that substantially encloses the sensor and communications module, wherein the acoustically transmissive encapsulation is of ingestible size. The multi-sensor array includes a plurality of acoustic transducers that receive an acoustic signal from a movable device, and a plurality of delays, wherein each delay is coupled to a corresponding acoustic transducer. Each delay may be adjusted according to a phase of a signal received by the corresponding acoustic transducer.

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INGESTIBLE ENDOSCOPIC OPTICAL SCANNING DEVICE

US20180353058

2018-12-13

An ingestible scanning device includes, in an embodiment, a capsule housing having a transparent window and sized so as to be ingestible, a photo-sensing array located within the capsule housing, a mirror located within the housing and oriented to direct an image from a surface outside the transparent window to the photo-sensing array, and a light source for illuminating the surface outside the transparent window.

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RADIAL SCANNER IMAGING SYSTEM

EP3300652

2018-04-04

According to an aspect, an ingestible scanning device is provided, comprising: an ingestible capsule housing having a transparent window; a photo-sensing array located within the ingestible capsule housing; and a stationary conical reflector, located within the ingestible capsule housing, configured to deflect an image into a circular band to project a toroidal shaped image onto the photo-sensing array.

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BATTERY OPERATED IMPLANTED CARDIAC STIMULATOR - HAS SIGNAL GENERATOR WITH D=A CONVERTER TO PROVIDE BASIC SIGNAL REPETITION RATE

FR2374024A1

1978-07-13

L'invention concerne un stimulateur cardiaque implantable avec programmation extérieure de fréquence. Il comporte deux contacts magnétiques commandés de l'extérieur, le premier par un champ magnétique faible et le second par un champ magnétique fort. Le second contact, lorsqu'il est fermé, applique des impulsions à un circuit de programmation comprenant un compteur qui progresse par un certain nombre d'états. A chacun de ces états correspond une fréquence de répétition prédéterminée des impulsions de stimulation. Lorsque le champ magnétique est supprimé, le compteur cesse de progresser, mais reste dans la position où il se trouve. Application au traitement des maladies cardiaques par stimulateur implanté.

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