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Susan Schober - InventionShare. Los Angeles, CA, US

Susan Schober Susan Schober

Co-Founder | Circuit Seed

Los Angeles, CA, UNITED STATES

Susie is an inventor and entrepreneur with expertise in the area of electrical engineering, specifically analog integrated circuit design

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Biography

Susie is an inventor and entrepreneur with expertise in the area of electrical engineering, specifically analog integrated circuit design. She has experience from the start to finish of an IC including the specifications, design, layout, simulation, photolithography, fabrication, testing, and commercialization of radio-frequency, mixed signal, and analog circuits and systems. Her interests include creating novel low power, high performance analog circuits for nanoscale CMOS technologies and the automation of analog IC design.

Areas of Expertise (6)

Complementary Current Field Effect Transistor (CiFET) Analog & Digital IC Design Integrated Circuit Design Cadence PCB Design CMOS

Accomplishments (15)

1ST Prize, Best Student Paper Award, IEEE VI LASCAS

2015

International Travel Grant Award, USC WiSE

2015

Scholar Travel Grant Award, USC Ming Hsieh Institute

2015

Conference Travel Grant Award, USC Department of Electrical Engineering-Electrophysics

2015

1ST Prize, Best Paper Award, USC-ISI Viterbi Graduate Student Symposium

2014

Graduate Research Assistantship, MOSIS

2014 - 2015

Graduate Research Assistantship, USC-ISI, National Semiconductor/Texas Instruments, DARPA, and NSF

2008 - 2013

Chair Doctoral Fellowship, USC Dept. of Electrical Engineering-Electrophysics

2006 - 2010

Viterbi Family Fund Engineering Scholarship, USC

2005 - 2006

1ST Prize, Senior VLSI Design Project Winner, USC EE477L

2005

Farr Engineering Scholarship, USC

2004 - 2005

SCion Scholarship, USC

2002 - 2005

Trojan Junior Auxiliary League Scholarship, USC

2002 - 2004

Marilyn Sion Environmental Awareness Scholarship

2002

OC Physics Student of the Year Award

2002

Education (5)

University of Southern California: Doctor of Philosophy, Electrical Engineering 2015

University of Southern California: Master of Science, Biomedical Engineering 2014

University of Southern California: Master of Science, Engineering Management 2010

University of Southern California: Master of Science, Electrical Engineering 2007

University of Southern California: Bachelor of Science, Electrical Engineering 2006

Affiliations (7)

  • USC Viterbi School of Engineering : Adjunct Lecturer
  • IEEE Student Member
  • Tau Beta Pi (TBP) Engineering Honor Society Member
  • Eta Kappa Nu (HKN) Electrical Engineering Honor Society Member
  • Alpha Omega Epsilon (AOE) Engineering Sorority Member
  • Society of Women Engineers (SWE) Member
  • USC Women in Science and Engineering (WiSE) Member

Languages (4)

  • English
  • Farsi
  • French
  • Spanish

Patents (32)

COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

WO2017019064

2017-02-02

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

US10211781

2019-02-19

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

EP3329598

2018-06-06

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

CA3031736

2017-02-02

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

CN10814121

2018-06-08

本发明涉及新颖及发明性复合装置结构,从而实现利用亚阈值操作的基于电荷的方法,以用于设计模拟CMOS电路。确切地说,本发明涉及基于对互补n型及p型电流场效应晶体管的固态装置,所述电流场效应晶体管中的每个具有两个控制端口,亦即低阻端口和栅控端口,而常规固态装置具有个控制端口,亦即栅控端口。这种新颖固态装置提供优于所述常规装置的各种改良。

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

KR20180034555

2018-04-04

본 발명은, 아날로그 CMOS 회로를 설계하기 위한, 서브-문턱 동작(sub-threshold operation)의 이점을 갖는 전하 기반 접근법을 가능하게 하는 신규하고 독창적인 복합 소자 구조에 관한 것이다. 특히, 종래의 고체 상태 소자는 하나의 제어 포트, 즉, 게이트 제어 포트를 갖는 반면, 본 발명은 두 개의 제어 포트, 즉, 저 임피던스 포트 및 게이트 제어 포트를 각각 갖는 n-형 및 p-형 전류 전계효과 트랜지스터의 상보적 쌍에 기초한 고체 상태 소자에 관한 것이다. 이 신규한 고체 상태 소자는 종래의 소자에 비해 다양한 개선을 제공한다.

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

WO2017105554

2017-06-22

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuites.

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

US10283506

2019-05-07

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

CN108140613

2018-06-08

本发明涉及对基于新颖及创造性复合装置结构的电流场效应晶体管和跨阻抗MOS装置的改进,所述复合装置结构实现基于电荷的利用亚阈值操作的方法,所述方法用于设计模拟CMOS电路。本发明进步涉及过饱和电流场效应晶体管(xiFET),其具有源极、漏极、扩散、第栅极和第二栅极端子,其中源极沟道界定于所述源极端子与所述扩散端子之间,漏极沟道界定于所述漏极端子与所述扩散端子之间。所述第栅极端子电容耦合到所述源极沟道;且所述第二栅极端子电容耦合到所述漏极沟道。所述扩散端子接收引起整个所述源极和漏极沟道中的扩散电荷密度的改变的电流。所述xiFET提供用于设计各种模拟电路的基本构建块。

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

WO2017019973

2017-02-02

The present invention relates to a multi-stage and feed forward compensated complimentary current field effect transistor amplifiers, enabling a charge-based approach that takes advantage of the exponential properties incurred in sub-threshold operation. A plurality of complimentary pairs of novel current field effect transistors are connected in series to form a multi-stage amplifier.

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

US20180226930

2018-08-09

The present invention relates to a multi-stage and feed forward compensated complimentary current field effect transistor amplifiers, enabling a charge-based approach that takes advantage of the exponential properties incurred in sub-threshold operation. A plurality of complimentary pairs of novel current field effect transistors are connected in series to form a multi-stage amplifier.

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

CN108141181

2018-06-08

本发明涉及种多级式且前馈补偿的互补电流场效应晶体管放大器,实现利用在亚阈值操作中引发的指数属性的基于充电的方法。新颖电流场效应晶体管的多个互补对串联连接以形成多级放大器。

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

WO2017019978

2017-02-02

The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET), and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel / W/L of drain channel).

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

US20180219519

2018-08-02

The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

CN108141180

2018-06-08

本发明涉及种用于低噪声电流放大器或跨阻抗放大器的新颖和创造性的复合装置结构。所述跨阻抗放大器包含:放大器部分,所述放大器部分使用对互补的新颖n型和p型电流场效应晶体管(NiFET和PiFET)来将电流输入转换为电压;以及使用另对互补的NiFET和PiFET的偏置产生部分。可通过源极沟道的宽度(W)长度(L)比与漏极沟道的宽度(W)长度(L)比的比率(源极沟道的W/L/漏极沟道的W/L)来配置和编程NiFET和PiFET的跨阻抗以及其增益。

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

WO2017019981

2017-02-02

Existing proportional to absolute temperature (PTAT)/ complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

US20180224878

2018-08-09

Existing proportional to absolute temperature (PTAT)/complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

CN108140614

2018-06-08

现有的与绝对温度成比例(PTAT)/与绝对温度互补(CTAT)参考电压电路需要种对准确度和对温度及湿度的不符合要求的灵敏度误差或变化进行匹配的较大组件计数和占地面积的精确装置。本发明涉及种用于这种基于对自偏置互补的n型和P型电流场效应晶体管的参考电压电路的新颖方法,所述方法提供轨道PTAT、轨道CTAT和模拟参考电压。

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SCALABLE INTEGRATED DATA CONVERTER

WO2017106835

2017-06-22

The present invention relates to an integrated data converter, in particular analog to digital converters (ADC) and digital to analog converters (DAC), using a charge-based approach. Complimentary pairs of current field effect transistors are used to form amplifiers for forming scalable ADCs and DACs are disclosed, including successive approximation data converters (ADCs and DACs), and pipe-lined data converters (ADCs and DACs).

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SCALABLE INTEGRATED DATA CONVERTER

EP3391544

2018-10-24

The present invention relates to an integrated data converter, in particular analog to digital converters (ADC) and digital to analog converters (DAC), using a charge-based approach. Complimentary pairs of current field effect transistors are used to form amplifiers for forming scalable ADCs and DACs are disclosed, including successive approximation data converters (ADCs and DACs), and pipe-lined data converters (ADCs and DACs).

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SCALABLE INTEGRATED DATA CONVERTER

CN108702155

2018-10-23

本发明涉及种集成数据转换器,具体地涉及使用基于电荷的方法的模数转换器(ADC)和数模转换器(DAC)。电流场效应晶体管的互补对用于形成可扩展ADC的放大器,并且公开了DAC,包含逐次逼近数据转换器(ADC和DAC)和流水线数据转换器(ADC和DAC)。

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SCALABLE INTEGRATED DATA CONVERTER

JP2019504585

2019-02-14

本発明は、集積データ変換器、特に、電荷に基づく手法を使用する、アナログデジタル変換器(ADC)及びデジタルアナログ変換器(DAC)に関する。スケーラブルADC及びDACを形成するための増幅器を形成するために使用される相補ペアの電流電界効果トランジスタが開示され、これは、逐次比較型データ変換器(ADC及びDAC)、及びパイプライン型データ変換器(ADC及びDAC)を含む。

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LOW NOISE SENSOR AMPLIFIERS AND TRANS-IMPEDANCE AMPLIFIERS USING COMPLEMENTARY PAIR OF CURRENT INJECTION FIELD-EFFECT TRANSISTOR DEVICES

WO2018098389

2018-05-31

This invention relates to low noise sensor amplifiers and trans-impedance amplifiers using a complementary pair of current injection field effect transistor (iFET) devices (CiFET). CiFET includes a N-type current field-effect transistor (NiFET) and a P-type current field-effect transistor (PiFET), each of the NiFET and PiFET has a source, a drain, a gate, and a diffusion (current injection) terminal (iPort). Each iFET also has a source channel with a width and a length between the source and diffusion terminal, and drain channel with a width and a length between the drain and the diffusion terminal. A trans-impedance of the CiFET device is adjusted by a ratio of width / length of source channel over width / length of drain channel of the iFET and supply power voltage. In one configuration, the gate terminals of the NiFET and PiFET are connected together to form a common gate. In another configuration that common gate is configured as a voltage input for a high input impedance mode. Output voltage swings around a common mode voltage.

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

WO2016118936

2016-07-28

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved / addressed by use with a charge transfer-based PLL charge pump.

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

US20170373697

2017-12-28

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

CA2973368

2016-07-28

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved / addressed by use with a charge transfer-based PLL charge pump.

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

WO2016118183

2016-07-28

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

US20180019757

2018-01-18

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

CA2974821

2016-07-28

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

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TRACK AND HOLD CIRCUIT

WO2018200482

2018-12-06

The present invention relates to an improvement to a track and hold circuit. A jitter-free track and hold function independent of signal amplitude is achieved by a circuit which fixes the sample voltage to the charge on a flying sampling capacitor and sets maintains that charge prior to isolation through applying application of the sample voltage to a utilization circuit. This may be done by adding an extra switch to the standard track and hold circuit and operating the switches in a timed sequence manner to provide the sample aperture based on the charge on the flying sampling capacitor common to the circuit.

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CHARGE-BASED PHASE LOCKED LOOP CHARGE PUMP

US8525564

2013-09-03

Charge-based charge pumps are described which include a switchable capacitor configured for connection to a voltage source, a ground, and a charge pump output. A first pair of switches include a first switch configured to connect the switchable capacitor to ground and a second switch configured to connect the switchable capacitor to the voltage source. A second pair of switches include a third switch configured to connect a first node, between the switchable capacitor and ground, to the charge pump output, and a fourth switch configured to connect a second node, between the switchable capacitor and the voltage source, to the charge pump output. Locked loop designs, such as phase locked loops or delay locked loops, are described that include charge-based charge pumps.

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ELASTOMERIC OPTICAL TACTILE SENSOR

WO2012129410

2012-12-27

A tactile sensor may include at least one light source and multiple light sensors within a common, protective housing. Each light sensor may be oriented to detect light originating from the light source. The housing may include flexible material that deforms in response to force applied to an external surface of the housing. In turn, this may cause changes in the intensity of light that is detected by the light sensors. A signal processing system may generate information that is representative of the magnitude of the applied force in at least two orthogonal directions based on the intensity of light detected by the light sensors. Each light sensor may be contained within a cavity in the housing. The cavity may be configured such that its geometry affects the sensitivity of the light sensor to the applied force.

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Selected Articles (5)

A 1.25mW 0.8-28.2GHz Charge Pump PLL with 0.82ps RMS Jitter in All-Digital 40nm CMOS International Symposium on Circuits and Systems (ISCAS 2015)

Susan Schober, John Choma

2015

This paper presents a wide-operating range analog phase locked loop (PLL) constructed from all-digital integrated circuit (IC) process components. Specifically, this work introduces 2 cutting-edge, scalable analog circuit designs for a charge pump (CP) and a voltage controlled oscillator (VCO). The ultra-low power and highly accurate CP circuit uses 6 minimum-sized transistors, a small metal interconnect capacitor, and, unlike the state-of-the-art, no current mirrors. The ring VCO has a reconfigurable, expandable structure and is capacitively tunable allowing for an exceptionally large frequency operating range of 0.8 to 28.2GHz making it suitable for variety of wireless and wireline applications. The PLL has been fabricated in a TSMC 40nm all-digital CMOS process and physically tested with a 0.5-1.2V supply. The fabricated PLL has an area of 0.0048mm 2 , consumes a maximum of 1.25mW, and has a 0.82 ±0.0275ps RMS jitter over the entire operating range.

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A Dual Reset D Flip-Flop Phase-Frequency Detector for Phase Locked Loops Iberchip

Susan Schober, John Choma

2015

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A Charge Transfer-Based High Performance, Ultra-Low Power PLL Charge Pump Latin American Symposium on Circuits and Systems (LASCAS 2015)

Susan Schober, John Choma

2015

This paper presents a high performance, ultra-low power scalable charge pump (CP) design for analog phase locked loops (PLLs). The compact CP circuit uses 4 minimum-sized transistor switches and a relatively small capacitor for transferring charge within the PLL to adjust the voltage controlled oscillator (VCO) frequency. Unlike the state of the art, the proposed CP design does not use current mirrors, has the ability to operate at very low voltages, and does not suffer from traditional mismatch errors due to its unique design. The fast switching action of the proposed CP allows for the use of a no-added delay D-flip flop (DFF) based phase-frequency detector (PFD) resulting in reduced PLL control loop delay and very low reference spurs in a PLL design. The proposed CP has been fabricated with a 1-10GHz PLL in TSMC all-digital 40nm CMOS process and physically tested with a variable 0.5-1.2V supply and a 50MHz-1GHz reference frequency. The charge pump has an active area of 0.0004mm 2 , consumes on average 250pW power, and has a 0.1-0.3° phase error, depending on the PLL frequency of operation.

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Drug Delivery Using Wireless MEMS Handbook of MEMS for wireless and mobile applications

Roya Sheybani, Susan M. Schober, Ellis Meng

2013

Drug delivery is essential for the treatment of chronic conditions. Implantable site-specific drug delivery devices offer direct delivery to the site of therapy, improving treatment outcomes while reducing side effects and overall associated healthcare costs. Microelectromechanical systems (MEMS) miniaturize infusion pumps such that they are implantable; wirelessly-powered to eliminate the use of bulky, limited lifetime batteries; and volume efficient. Wireless communication allows remote monitoring of device status and performance, and remotely initiated changes to the drug regimen for patient tailored therapy. Requirements for a MEMS drug delivery device with wireless powering and data communication are presented along with an example of such a device.

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A Capacitively Phase-Coupled Low Noise, Low Power 0.8-to-28.2GHz Quadrature Ring VCO in 40nm CMOS New Circuits and Systems Conference (NEWCAS 2015)

Susan Schober, John Choma

2015

This paper presents a novel tunable wide-operating range capacitively phase-coupled low noise, low power ring-based voltage controlled oscillator (VCO) for use in multi-GHz phase-locked loops (PLLs). The basic building blocks of the ring oscillator (RO) design are discussed along with a technique to expand the VCO to a variety of phases and frequencies without the use of physical inductors. Improved performance with minimal phase noise are achieved in this ring VCO design through distributed passive-element injection locking (IL) of the staged phases via a network of symmetrically placed metal interconnect capacitors. Using this method, a 0.8-to-28.2 GHz quadrature ring VCO was designed, fabricated, and physically tested with a PLL in an all-digital 40nm TSMC CMOS process. Most notably the proposed quadrature VCO occupies an area of 0.0024mm2, consumes a power of 0.88mW at a 1.0V supply voltage, and possesses a phase noise of -124.5dBc/Hz at the 10MHz offset for a carrier frequency of 28.0GHz.

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